New ContributorHow to simulate PCIe and DDR in ModelSim
Hello,
I am reposting, in a new thread as suggested to me.
I am trying to simulate PCIe_DDR4 example provided for Terasic DE5a-NET DD4. I have made a modification to the project. After opening it in Quartus Prime Pro [linux: 22.4.0] and going to Platform Designer [22.4 Build 94] I add a custom counter logic as a component and an Avalon FIFO [altera_avalon_fifo] in the System Viewer. Just the counter and the FIFO together were simulated in ModelSim and found to be working correctly.
The Avalon FIFO will connect to the pipe stage [altera_avalon_mm_bridge] and write data to the DDR4 memory. I want to verify this in simulation before proceeding to hardware verification.
I am unclear as how to do this and would appreciate any recommendations. How can I simulate an environment where My Counter input is going through the FIFO and being written down to the DDR memory? The PCIe_DDR4 example has several ip blocks:
altera_pcie_a10_hip
altera_avalon_pio
altera_avalon_mm_bridge
altera_emif
I would like to inspect signals through these IPs and confirm read/writes happening correctly.
Please let me know if you would require any more information?
