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You certainly have done a good GUI and spent a lot lot of time to get to that stage. My first point is this "could there be a bug in the idea itself?".
my second point is this: is it verilog or boxes? if boxes then what is diffeent from schematic? Or do you mean you design by boxes but can simulate boxes or verilog?
Beginners = Uni students and are tied up to their professors choice. However, I do wish you success seriosly because you are far more creative than many of us.
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Thanks for your reply!
Here is the answers:
1. The design goal is try to form a visual design method, but is not visualizing verything. We consider each module as a box with interfaces to other boxes, and algorithm should be manually input! The designer can use verilog to describe their algorithm inside each boxes. If you have any suggestion on the design or feel there is a bug in idea itself, why not tell us so we can improve it.
2. The box represents verilog "module", but algorithms use verilog language directly! Schematic is more detail, but Robei's model is abstract. After your design, it will translated to verilog language, and do the simulation.
3.Robei is entry level tool, student can also design with Robei, taking the code out to other vendor tools for synthesis! So it only try to verify your design and completed at simulation level.
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