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Honored Contributor
Honored ContributorHow to set multicycle for this design?
In my design, all clocks are clka (100 MHz), but clock enables are used to make registers change at 25 MHz or 6.25 MHz. The signal path is reg1(clka,100MHz)->reg2(enable to 25 MHz, clocked by cl...
Altera_ForumHonored Contributor
Honored ContributorHi rbugalho, Thanks a lot for the detailed and patient explaination. I got it finally.
When data goes from reg1 (no enable clock) to reg2 (enabled clock), only when launch register launches data several clocks before an output register latches it, a multicycle can be set to reg2. Thanks a lot again!
