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Honored Contributor
Honored ContributorHow to set multicycle for this design?
In my design, all clocks are clka (100 MHz), but clock enables are used to make registers change at 25 MHz or 6.25 MHz. The signal path is reg1(clka,100MHz)->reg2(enable to 25 MHz, clocked by cl...
Altera_ForumHonored Contributor
Honored ContributorHI rbugalho,
I still have questions about multicycle setting from reg1 (100 MHz) to reg2(enabled to 25MHz). I have read many documentations, which say that from high frequency to low frequency, the path can be set to multicycle. Here is an example: http://www.altera.com/support/examples/timequest/exm-tq-clock-enable.html#figure1 (http://www.altera.com/support/examples/timequest/exm-tq-clock-enable.html#figure1) But you said it can not be set to multicycle path, can you explain the conflictions between your reason and the example?
