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Honored Contributor
Honored ContributorHow to set multicycle for this design?
In my design, all clocks are clka (100 MHz), but clock enables are used to make registers change at 25 MHz or 6.25 MHz. The signal path is reg1(clka,100MHz)->reg2(enable to 25 MHz, clocked by cl...
Altera_ForumHonored Contributor
Honored ContributorThanks very much again for the information. It is very helpful for me.
Now I'm going to use the second solution, from bit to bit. When I do this for {set n 192} {$n <= 287} {incr n}{ set_multicycle_path -from {spu:i_spu|data_processing_chain:i_data_processing_chain|tp1_data_receiver:i_tp1_data_receiver|rx_tapering:i_rx_tapering|rx_tapering_core:i_rx_tapering_core|data_out_tmp[$n]} -to {spu:i_spu|data_processing_chain:i_data_processing_chain|tp1_data_receiver:i_tp1_data_receiver|rx_tapering:i_rx_tapering|rx_tapering_core:i_rx_tapering_core|data_out[$n]} -setup 3 } It complain no variable n exasits. I believe this is because the bracket of the path. After I removed bracket, like this: for {set n 192} {$n <= 287} {incr n}{ set_multicycle_path -from spu:i_spu|data_processing_chain:i_data_processing_chain|tp1_data_receiver:i_tp1_data_receiver|rx_tapering:i_rx_tapering|rx_tapering_core:i_rx_tapering_core|data_out_tmp[$n] -to spu:i_spu|data_processing_chain:i_data_processing_chain|tp1_data_receiver:i_tp1_data_receiver|rx_tapering:i_rx_tapering|rx_tapering_core:i_rx_tapering_core|data_out[$n] -setup 3 } It complains extra characters after close-brace, I do not understand why, how can I set this?
