How to set multicycle for this design?

Suggestion 1: Use keepers.

Create a combinatory signal for each of the enable cases; mark is as a "keeper"; write your logic based on it and write your SDC based on it's fanouts.

signal enable_0 : std_logic;
attribute keep : boolean;
atrribute keep of signal enable_0 is true;
...
enable_0 <= '1' when clock_enable_counter = "00" else '0';
...
-- if clock_enable_counter = "00" then
if enable_0 = '1' then
...

Then you should be able to get the fanouts of it.

Suggestion 2: Set it bit by bit, using loops.

The SDC file is a TCL script, you can do whatever you need.

for{set n 0}{$n <= 95}{incr n}{
set_multicycle_path -from reg2 -to reg3 ....