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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to set multicycle for this design?

In my design, all clocks are clka (100 MHz), but clock enables are used to make registers change at 25 MHz or 6.25 MHz. The signal path is reg1(clka,100MHz)->reg2(enable to 25 MHz, clocked by cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Suggestion 1: Use keepers.

Create a combinatory signal for each of the enable cases; mark is as a "keeper"; write your logic based on it and write your SDC based on it's fanouts. 

signal enable_0 : std_logic;
attribute keep : boolean;
atrribute keep of signal enable_0 is true;
...
enable_0 <= '1' when clock_enable_counter = "00" else '0';
...
-- if clock_enable_counter = "00" then
if enable_0 = '1' then
...

Then you should be able to get the fanouts of it.

Suggestion 2: Set it bit by bit, using loops.

The SDC file is a TCL script, you can do whatever you need. 

for{set n 0}{$n <= 95}{incr n}{
set_multicycle_path -from reg2 -to reg3 ....