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Honored Contributor
Honored ContributorHow to set multicycle for this design?
In my design, all clocks are clka (100 MHz), but clock enables are used to make registers change at 25 MHz or 6.25 MHz. The signal path is reg1(clka,100MHz)->reg2(enable to 25 MHz, clocked by cl...
Altera_ForumHonored Contributor
Honored ContributorThanks very much, I got it finally!
I have a question about how to set different multicycle in an easy way. In my case, the reg2 actually has 384 bits. And reg2 (95 downto 0) is enabled when clock_enable_counter = 0, Reg2 (191 downto 96) is enabled when clock_enable_counter =1, Reg2(287 downto 192) is enabled when clock_enable_counter =2, Reg2(383 downto 288) is enabled when clock_enable_counter =3, It is not possible to set bit by bit. I’m thinking about something like this: set_multicycle_path 2 -to [get_fanouts [get_pins enable_reg|q*] \ -through [get_pins -hierarchical *|*ena*]] -end -setup But in my case, every bit of reg2 is enabled by clock_enable_counter, so this may not work for my case. Does anybody have any sugguestion?
