How to set multicycle for this design?

Thanks very much, I got it finally!

I have a question about how to set different multicycle in an easy way.

In my case, the reg2 actually has 384 bits.

And reg2 (95 downto 0) is enabled when clock_enable_counter = 0,

Reg2 (191 downto 96) is enabled when clock_enable_counter =1,

Reg2(287 downto 192) is enabled when clock_enable_counter =2,

Reg2(383 downto 288) is enabled when clock_enable_counter =3,

It is not possible to set bit by bit. I’m thinking about something like this:

set_multicycle_path 2 -to [get_fanouts [get_pins enable_reg|q*] \

-through [get_pins -hierarchical *|*ena*]] -end -setup

But in my case, every bit of reg2 is enabled by clock_enable_counter, so this may not work for my case.

Does anybody have any sugguestion?