Honored Contributor
Honored ContributorThe first point has no meaning for the storage method, I think. Intermediate data buffering (e.g. by a FIFO) would be necessary in most cases anyway.
I see, that it's difficult to connect the required memory with a 780 pin package (you also didn't mention this before). A 64 Bit DDR RAM would be ususally connected through x8 DQS groups, but it's not possible using one FPGA side, that has only 7 of it. Also other IO constraints have to be considered when selecting a suitable interface method, not known in detail. Generally, DDR RAM offers the highest pin density in connecting external storage and also lowest relative cost. If it's not possible, you should check the SSRAM variant as well. If both fail, you need a larger package.
