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Altera_Forum
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17 years ago

How to route output clock of alt2gxb to a pll?

Hi, The error information is "Error: Clock input port inclk[0] of PLL "pllo:u_pllo|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks for reply.

Its my first time to run altera fpga.

do you have any suggestions about my requirement?

best regards,

Jimmy

note, I try to output gxb clock outside fpga chip and connect it back to a clock pin , then

atlpll can generate x1 and x(1/2) in-phase clock. But timing between gxb:clk and pll:x1/x(1/2) clock cannot be check exactly.