Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to route output clock of alt2gxb to a pll?
Hi, The error information is "Error: Clock input port inclk[0] of PLL "pllo:u_pllo|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Cl...
Altera_ForumHonored Contributor
Honored ContributorThanks for reply.
Its my first time to run altera fpga. do you have any suggestions about my requirement? best regards, Jimmy note, I try to output gxb clock outside fpga chip and connect it back to a clock pin , then atlpll can generate x1 and x(1/2) in-phase clock. But timing between gxb:clk and pll:x1/x(1/2) clock cannot be check exactly.
