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Altera_Forum
Honored Contributor
19 years agoHow to remove glitches on Incoming signals ?
Hi *, I have signals coming to the FPGA which are not clean . All these signals are asynchronous signals. I want to remove the glitches on these signals and then feed them to the inputs o...
Altera_Forum
Honored Contributor
19 years agoHC14 or similar is a great idea in analog land, for detecting edges. A minimum width threshold (glitch detector) is a useful block to have in digital land, especially if your minimum width is tied to registers (not hardwired); you can then tune the glitch rejection if need be.
A combination of both is even better. Note if you have a very short asynchronous pulse and want to register that to internal logic, the likelihood is you'll get some occasional wierd effects in the digital domain, perhaps missing some pulses altogether. Chain several FFs together, all clocked with global clock of course, even as many as 6-8 FFs, to have a better chance of getting a clean input. (I can't remember why this is so; can anyone explain this? something to do with delays in the implementation of the gates. There's an app note about it somewhere.)