Forum Discussion
BXia
Occasional Contributor
Occasional ContributorHow to reduce the high fan out nets in Quartus project?
Hi Intel FPGA supporter, We found there are high fan out nets in our project, is there any way to reduce the high fan out nets? Please see the attached image. Thanks in advanced!
sstrell
Super Contributor
Super ContributorThere are many methods for reducing high fanout. Register duplication is usually the main solution. Lots of resources available for this:
https://learning.intel.com/Developer/learn/courses/216/design-evaluation-for-timing-closure
https://learning.intel.com/Developer/learn/courses/237/best-design-practices-for-timing-closure
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