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Occasional Contributor

1 year ago

How to reduce the high fan out nets in Quartus project?

Hi Intel FPGA supporter, We found there are high fan out nets in our project, is there any way to reduce the high fan out nets? Please see the attached image. Thanks in advanced!

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sstrell

Super Contributor

1 year ago

There are many methods for reducing high fanout. Register duplication is usually the main solution. Lots of resources available for this:

https://www.intel.com/content/www/us/en/docs/programmable/683641/24-2/duplicate-registers-for-fan-out-control.html

https://learning.intel.com/Developer/learn/courses/216/design-evaluation-for-timing-closure

https://learning.intel.com/Developer/learn/courses/237/best-design-practices-for-timing-closure

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How to reduce the high fan out nets in Quartus project?

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