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Altera_Forum's avatar
Altera_Forum
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12 years ago

How to Program Cyclone V SoC Dev Kit EPCQ256

I am looking for directions on how to program the EPCQ256 device on the Cyclone V SoC Dev Kit Board. I tried to accomplish this by generating a jic programming file and use the quartus programmer to do the programming. It succeeds at configuring the fpga, but fails when it goes to program the EPCQ256 device. I tried setting MSEL[4:0] to 10010 and 10011, but neither seems to work. I also tried generating the jic with AS x1 and x4, but both settings produce the same error results. Something that is making this hard for me to debug is I'm not sure where the programmer's error messages are sent. In older versions of quartus, the programmer error messages were sent to the quartus message window, but that doesn't seem to be true for 13.0sp1. Another thing that I'm not sure of is AS x1 vs. x4. From the datasheet, the EPCQ256 can do both modes. What determines which mode is being used?

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    MSEL[4..0]10010 Fast AS Mode can work well, as x 1 is lower speed configuration mode. if choose this ,after power on, the fpga configuration will not influence the HPS boot. if x4,it will influence it.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Peli, I'm not sure what is wrong. Probably some little thing that once I understand, will make it all work. Rarely do I get to blame it on the hardware. Right now I'm working on a different problem. So this one will have to wait until I come back to it, but I will find out the answer sooner or later. Once I do, I'll update this thread with what I learn.

    Thanks

    -kstolp
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    A couple of service requests to Altera revealed that the Max V component (U19) responsible for controlling FPGA configuration comes with a factory load that does not behave correctly when MSEL is set to one of the active serial configuration schemes. The Cyclone V SoC Development Board Reference Manual contains the following paragraph:

    "By default, this board has a FPP configuration scheme setting. The MAX_AS_CONF pin needs to be driven from the MAX V to enable the bus switch (U13) to isolate the EPCQ flash (U20) from the configuration bus. This happens when MSEL is 10010 or 10011."

    According to this paragraph, the MAX V (U19) should assert the MAX_AS_CONF pin when MSEL is 10010 or 10011. Both of these MSEL settings are active serial configuration schemes. Active serial is the configuration scheme used to configure the FPGA from the EPCQ256 device, which is the device I have been trying to program with a JIC file. The problem is the factory load for U19 does not behave as indicated in this paragraph from the reference manual. Altera did provide me with a programming file (.pof) for a newer version of the Max V design that does behave correctly. This required me to use the quartus programmer to reprogram U19. After reprogramming U19, I was able to program the EPCQ256 device using a JIC file and the quartus programmer. After the EPCQ256 device was programmed, the FPGA was able to configure itself from the EPCQ256 device.

    As a side note, I was also able to use the sof2flash, nios2-configure-sof, and nios2-flash-programmer commands from a Nios-II command shell to program the EPCQ256 as well. This does require an FPGA sof programming file with a nios2 processor.

    So Peli, it turned out to be a hardware problem as you predicted. Maybe what I've learned will help someone else?
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Hello,

    --- Quote Start ---

    Altera did provide me with a programming file (.pof) for a newer version of the Max V design that does behave correctly. This required me to use the quartus programmer to reprogram U19

    --- Quote End ---

    Could you share that pof file? Because we are also facing same issue here.

    Regards,

    Bhaumik
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Glad you solved your problem. My original post was 3 years ago. A little hard to remember all the details. I went back and looked at what Altera gave me, and it looks like it was quartus design files for the Max5 device. A very simple design with one pin tied to GND. I added a couple other pins to light up some LED's to indicate that the Max5 and Cyclone5 devices were configured. I had to compile the design to get the pof. Well, have fun.