how to place an input signal on DE2 FPGA

i have a problem with my project..

my project is about implementing FIR filter using Verilog HDL

the problem that occur is when i want to implement the project on DE2 FPGA board.. i dont have idea how to generate an input signal to test the FIR filter on the FPGA and how i want to see the output that had been filtered.. pls somebody help me.. i really appreciate your thought about this:(