Forum Discussion
Altera_Forum
Honored Contributor
12 years agosorry kaz ,
but i need your really help counter count the number of input samples then the counter output (n) and i want to check if the numbers of samples is even do that (n*n) or if odd make that ((n*n)-1). (dis) signal will have values as (1,6,9,8,.....100) and the second signal (n) will have values as (0,2,8,9.......,200) and i want to fetch the two last outputs from the two signal (100,200) and divide 100/200.how can i write it in vhdl and how can overcome the divide by zero error. i want help plz.