How to measure distance between two data

first you need to have a ram component. You can use inference as below or instantiate altera's ram

it is simple dual (separate read addr/write addr)

library ieee;
use ieee.std_logic_1164.all;
entity wr_rd_ram is
    port(
        clk      : in  std_logic;
        we       : in  std_logic;
        wr_data  : in  std_logic_vector(7 downto 0);
        wr_addr  : in  integer range 0 to 255;
        rd_addr  : in  integer range 0 to 255; 
        rd_data  : out std_logic_vector(7 downto 0)
         );
end entity;
architecture rtl of wr_rd_ram is
type mem is array(255 downto 0) of std_logic_vector(7 downto 0);
signal ram : mem;
begin
process(clk)
begin
if(rising_edge(clk)) then
   if(we = '1') then
       ram(wr_addr) <= wr_data;
   end if;
   rd_data <= ram(rd_addr);
end if;
end process;
end rtl;

then top level can be something as below. This is not functionally accurate but should give you guidance. You need to simulate and

adjust latency issues.

library ieee;
use ieee.std_logic_1164.all;
entity test is
    port(
        rst      : in  std_logic;
        clk      : in  std_logic;
        we       : in  std_logic;
        wr_data1 : in  std_logic_vector(7 downto 0);
        wr_data2 : in  std_logic_vector(7 downto 0);
        wr_addr  : in  integer range 0 to 255;
        distance : out integer range 0 to 255;
        vout     : out std_logic;
        no_match : out std_logic
         );
end entity;
architecture rtl of test is
signal rd_data1 : std_logic_vector(7 downto 0);
signal rd_data2 : std_logic_vector(7 downto 0);
signal rd_addr1 : integer range 0 to 255 := 0;
signal rd_addr2 : integer range 0 to 255 := 0;
type states is (s0,s1,s2);
signal state: states;
component wr_rd_ram
    port(
        clk      : in  std_logic;
        we       : in  std_logic;
        wr_data  : in  std_logic_vector(7 downto 0);
        wr_addr  : in  integer range 0 to 255;
        rd_addr  : in  integer range 0 to 255; 
        rd_data  : out std_logic_vector(7 downto 0)
         );
end component;
begin
ram1:wr_rd_ram
    port map(
        clk      => clk,
        we       => we,
        wr_data  => wr_data1,
        wr_addr  => wr_addr,
        rd_addr  => rd_addr1, 
        rd_data  => rd_data1
         );
ram2:wr_rd_ram
    port map(
        clk      => clk,
        we       => we,
        wr_data  => wr_data2,
        wr_addr  => wr_addr,
        rd_addr  => rd_addr2, 
        rd_data  => rd_data2
         );
process(rst,clk)
begin
if rst = '1' then
    state <= s0;
    vout <= '0';
    no_match <= '0';
    distance <= 0;
elsif rising_edge(clk) then
   vout <= '0';
   no_match <= '0';
   case state is
      when s0 =>
        rd_addr2 <= rd_addr2 + 1;
        if rd_data1 = rd_data2 then
           state <= s1;
           distance <= rd_addr1 - rd_addr2;
           vout <= '1';
        elsif rd_addr2 = 255 then
           rd_addr2 <= 0;
           state <= s2;
        end if;
 
      when s1 =>
        rd_addr1 <= rd_addr1 + 1;
        rd_addr2 <= 0;
        state <= s0;
      when s2 => 
         no_match <= '1';
         state <= s0;
      when others => null;
   end case;
end if;
end process;
end rtl;