How to measure distance between two data

---However you need to read each ram separately

i correct the code to read from each ram,does it is correct??

--and you need distance to be output successively as a stream.

how i can do that??

--- you need to read location 0 first and keep it till all locations of ram2 are checked and so on.

may i can do that by using function ''='' for equality or std_match (i try to do that) , but it is the correct way??

in the code below

library ieee;

use ieee.std_logic_1164.all;

--use ieee.std_logic_unsigned.all;

use IEEE.numeric_std.all;

entity test is

port

(

data_a : in std_logic_vector(7 downto 0);

data_b : in std_logic_vector(7 downto 0);

addr_a : in std_logic_vector(7 downto 0);

addr_b : in std_logic_vector(7 downto 0);

we_a : in std_logic := '1';

we_b : in std_logic := '1';

clk : in std_logic;

Re_a :in std_logic := '1';

Re_b :in std_logic := '1';

q_a : out std_logic_vector(7 downto 0);

q_b : out std_logic_vector(7 downto 0);

distance : out std_logic_vector(7 downto 0)

);

end test;

architecture rtl of test is

type memory_t is array(63 downto 0) of std_logic_vector(7 downto 0);

signal ram1, ram2 : memory_t;

signal read_addr_a : std_logic_vector(7 downto 0);

signal read_addr_b : std_logic_vector(7 downto 0);

signal q_a_int : std_logic_vector(7 downto 0);

signal q_b_int : std_logic_vector(7 downto 0);

begin

-- Port A

----write to port A

process(clk)

begin

if(clk='1'and clk'event) then

if(we_a = '1') then

ram1(to_integer(unsigned(addr_a))) <= data_a;

end if;

read_addr_a <= addr_a;

end if;

end process;

---read from port A

process(clk,Re_a)

begin

if (Re_a ='1') then

q_a_int <= ram1(to_integer(unsigned(read_addr_a)));

end if;

end process;

-------------------------------------------------------

-- Port B

--write to port B

process(clk)

begin

if(rising_edge(clk)) then

if(we_b = '1') then

ram2(to_integer(unsigned(addr_b))) <= data_b;

end if;

read_addr_b <= addr_b;

end if;

end process;

---read from port B

process(clk,Re_b)

begin

if (Re_b = '1') then

q_b_int <= ram2(to_integer(unsigned(read_addr_b)));

end if;

end process;

----------------------

process(clk)

begin

read_addr_a <= X"00"; --reset the address value for reading from memory location "0"

process(clk)

begin

if(rising_edge(clk)) then

if (std_match(q_a_int,q_b_int)) then

distance <= std_logic_vector(unsigned(addr_a)- unsigned (addr_b));

end if;

end if;

end process;

q_a <= q_a_int;

q_b <= q_b_int;

end rtl;

you also need address to be converted to signed adding sign bit.