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Altera_Forum
Honored Contributor
12 years agoI have corrected your code. see below
However you need to read each ram separately and you need distance to be output successively as a stream. i.e. you need to read location 0 first and keep it till all locations of ram2 are checked and so on. currently you are just reading on write address. you also need address to be converted to signed adding sign bit...
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity test is
port
(
data_a : in std_logic_vector(7 downto 0);
data_b : in std_logic_vector(7 downto 0);
addr_a : in std_logic_vector(7 downto 0);
addr_b : in std_logic_vector(7 downto 0);
we_a : in std_logic := '1';
we_b : in std_logic := '1';
clk : in std_logic;
q_a : out std_logic_vector(7 downto 0);
q_b : out std_logic_vector(7 downto 0);
distance : out std_logic_vector(7 downto 0)
);
end test;
architecture rtl of test is
type memory_t is array(63 downto 0) of std_logic_vector(7 downto 0);
signal ram1, ram2 : memory_t;
signal q_a_int : std_logic_vector(7 downto 0);
signal q_b_int : std_logic_vector(7 downto 0);
begin
-- Port A
process(clk)
begin
if(rising_edge(clk)) then
if(we_a = '1') then
ram1(to_integer(unsigned(addr_a))) <= data_a;
end if;
q_a_int <= ram1(to_integer(unsigned(addr_a)));
end if;
end process;
-- Port B
process(clk)
begin
if(rising_edge(clk)) then
if(we_b = '1') then
ram2(to_integer(unsigned(addr_b))) <= data_b;
end if;
q_b_int <= ram2(to_integer(unsigned(addr_b)));
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if (std_match(q_a_int,q_b_int)) then
distance <= std_logic_vector(unsigned(addr_a)- unsigned (addr_b));
end if;
end if;
end process;
q_a <= q_a_int;
q_b <= q_b_int;
end rtl;