How to measure distance between two data

sorry, kaz

i tried many times by many ways but it can't be solved

what is the mistake,and what is the correct way

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use IEEE.numeric_std.all;

entity true_dpram_sclk is

port

(

data_a : in std_logic_vector(7 downto 0);

data_b : in std_logic_vector(7 downto 0);

addr_a : in std_logic_vector(7 downto 0);

addr_b : in std_logic_vector(7 downto 0);

we_a : in std_logic := '1';

we_b : in std_logic := '1';

clk : in std_logic;

q_a : out std_logic_vector(7 downto 0);

q_b : out std_logic_vector(7 downto 0);

distance: out std_logic_vector(7 downto 0)

);

end true_dpram_sclk;

architecture rtl of true_dpram_sclk is

-- Build a 2-D array type for the RAM

subtype word_t is std_logic_vector(7 downto 0);

type memory_t is array(63 downto 0) of word_t;

-- Declare the RAM

shared variable ram : memory_t;

signal a_output:std_logic_vector(7 downto 0 );

signal b_output:std_logic_vector(7 downto 0);

signal d :std_logic_vector(0 to 7);

begin

-- Port A

process(clk)

begin

if(rising_edge(clk)) then

if(we_a = '1') then

ram(conv_integer (addr_a)) := data_a;

end if;

a_output <= ram(conv_integer (addr_a));

end if;

q_a <= a_output;

end process;

-- Port B

process(clk)

begin

if(rising_edge(clk)) then

if(we_b = '1') then

ram(conv_integer (addr_b)) := data_b;

end if;

b_output <= ram(conv_integer (addr_b));

end if;

q_b <= b_output;

if (std_match(a_output(0),b_output(0) )) then

d<= std_logic_vector(signed(addr_a(0))- signed (addr_b(0))); -----error The expression can not be converted to type signed.

end if;

distance <= d;

end process;

end rtl;