Forum Discussion
lambert_yu
Contributor
ContributorHow to make phase compensation between two clocks
Hi all, fpga type : 10ax115n3f45i1sg quartus : quartus 18.0.0 standard I have one design as below: pll pll_inst(.rst(), .refclk(), .outclk1(), .outclk2(),.outclk3(),.outclk4());//the o...
TingJiangT_IntelContributor
ContributorHi there, could you help upload your project for investigation? You can remove all RTL files for confidentiality but please make sure it can open timing analyzer and apply changes in other machines. Thanks
