Contributor
Super ContributorYou may use below multicycle constraints for fast-to-slow and slow-to-fast clock:
1) fast-to-slow clock :
set_multicycle_path -setup -from launch_clk(fast) -to latch_clock(slow) -start N
set_multicycle_path -hold -from launch_clk(fast) -to latch_clock(slow) -start N-1
2) slow-to-fast clock :
set_multicycle_path -setup -from launch_clk(slow) -to latch_clock(fast) -end N
set_multicycle_path -hold -from launch_clk(slow) -to latch_clock(fast) -end N-1
When you specify a multicycle path with a value of 1, it essentially means that the timing path is expected to be completed within one clock cycle, which is the default behavior.
Regards,
Richard Tan
ContributorHi, Richard
For the constrains :
set_multicylce_path -from [get_clocks {clock_fast_gl}] -to [get_clocks [clock_slow_gl]} -setup -start 1
set_multicylce_path -from [get_clocks {clock_fast_gl}] -to [get_clocks [clock_slow_gl]} -hold-end 1
set_multicylce_path -from [get_clocks {clock_slow_gl}] -to [get_clocks [clock_fast_gl]} -setup -start 1
set_multicylce_path -from [get_clocks {clock_slow_gl}] -to [get_clocks [clock_fast_gl]} -hold -end 1
I want to used to the below case
fast-> slow
slow -> fast
And in the previous email, I think the setup and holdup timing analysis follows the above multicycle path constrains.
1) But I don't know if it's enough or correct ? Besides, for the fast clock, there's 3 selection; and slow clock has 3 selection.
fast clock: 100M/50M/25M; slow clock : 50M/25M/12.5M, they all comes from the same PLL output.
fast_clock = sel == 2 ？ 100M : sel==1 ? 50M : 25M;
slow_clock = sel == 2 ? 50M : sel == 1 ? 25M : 12.5M;
use clkctrl IP, force fast_clock and slow clock use global clock routing.
2) But from the result of synthesis, they can not keep the phase relationship between each other. For example, in the above picture, the phase between fast_clock and slow_clock aligns to each other. after synthesis, there's phase shift. How could I keep this or there's no solution? (I tried to use dynamic phase adjustment, but it's hard to find one setting to achieve my goal.
BRs,
Lambert
