Contributor
Super ContributorWhere are the rest of your timing constraints that define the clocks themselves (create_clock, create_generated_clock, etc.)?
Also, a multicycle setup constraint of 1 does nothing because that's the default. As such, a multicycle hold of 1 won't work correctly because it's supposed to be based off a setup multicycle. Also, you've misspelled "multicycle" in all those constraints so I don't know if you copy/pasted this from your .sdc or just manually typed it.
Can you show more complete code or timing analyzer reports or timing waveforms of what you expect vs. what you are seeing?
ContributorHi, sstrell
I'm sorry that I made you confusion.
///clock constrains:
create_clock -name clk -periond 16.000 -waveform {0.000 8.000} [get_ports {clk}] -add
create_clock -name clock_fast_gl -period 8.000 [get_pins {clock_buf_inst|altclkctrl_0|clock_buf_altclkctrl_180_76rtb7q_sub_component|sd1|outclk}]
create_clock -name clock_slow_gl -period 16.000 [get_pins {clock_buf_inst|altclkctrl_0|clock_buf_altclkctrl_180_76rtb7q_sub_component|sd1|outclk}]
derive_pll_clocks
///multicycle
set_multicylce_path -from [get_clocks {clock_fast_gl}] -to [get_clocks [clock_slow_gl]} -setup -start 1
set_multicylce_path -from [get_clocks {clock_fast_gl}] -to [get_clocks [clock_slow_gl]} -hold-end 1
set_multicylce_path -from [get_clocks {clock_slow_gl}] -to [get_clocks [clock_fast_gl]} -setup -start 1
set_multicylce_path -from [get_clocks {clock_slow_gl}] -to [get_clocks [clock_fast_gl]} -hold -end 1
Yes, for setup items , it should use the default setup check. But for hold items, I made sure it make sense just from the timing analysis (as below figure).
/// fast to slow (setup)
///fast to slow (hold)
///slow to fast (setup)
///slow to fast (hold)
(From slow clock domain to fast clock domain, I think if the setup timing (from current launch clock edge to next latch clock edge) and hold timing (from current launch clock edge to previous latch clock edge ) are all satisfy, the setup and holdup timing for the current latch clock edge (which is located at between next latch edge and previous latch edge) will be satisfy.
The timing are all satisfy, but I don't know why clock_fast_gl and clock_slow_gl could not be keep in phase after altclkctrl IP.
If you need more information, you could tell me. Thanks!
BRs,
Lambert
