Altera_ForumHonored Contributor15 years agohow to make a testbench Dear all, Can anyone give me simple example on how to make a testbench in vhdl using ModelSim. thanks
Altera_ForumHonored Contributor15 years agohttp://www.tkt.cs.tut.fi/kurssit/1210/k06/luennot/lect5.pdf a good introduction but you don't necessarily need the configuration feature.
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