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Altera_Forum
Honored Contributor
15 years agohow to make a testbench
Dear all,
Can anyone give me simple example on how to make a testbench in vhdl using ModelSim. thanks2 Replies
- Altera_Forum
Honored Contributor
Dear kaz,
Thanks for reply.I will study the document first. - Altera_Forum
Honored Contributor
a good introduction but you don't necessarily need the configuration feature.