Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to let FPGA get access to HPS pins
I've got an Arrow SOCkit and it has a USB-UART connected to the HPS' pins, but I'd like to access the UART from the FPGA logic. Is this possible? If so how is it done? Thank you!
SanaGuezguez
New Contributor
New ContributorHello everyone,
I'm having an issue implementing an FPGA to HPS communication and vice versa. I'm using the MitySOM 5csx with a Cyclone V SoC. The purpose of the project is to setup the bridges between the HPS and FPGA in such a way that a program running on the HPS will send data to the FPGA which will process it and return a result. I've generated a QSYS design, composed by the HPS (with Cyclone V settings), two fifos, a clock bridge, a clock and an SDRAM.
When I run the simulation and synthesis and the TCL pin-assignment script generated by Qsys everything works fine. The issue comes when I try to compile the whole design, because I get an error message saying there are 375 IO input pads in the design, but only 331 IO input pad locations are available on the device. I don't know what I'm missing or doing wrong. Any suggestion is welcome
I'm having an issue implementing an FPGA to HPS communication and vice versa. I'm using the MitySOM 5csx with a Cyclone V SoC. The purpose of the project is to setup the bridges between the HPS and FPGA in such a way that a program running on the HPS will send data to the FPGA which will process it and return a result. I've generated a QSYS design, composed by the HPS (with Cyclone V settings), two fifos, a clock bridge, a clock and an SDRAM.
When I run the simulation and synthesis and the TCL pin-assignment script generated by Qsys everything works fine. The issue comes when I try to compile the whole design, because I get an error message saying there are 375 IO input pads in the design, but only 331 IO input pad locations are available on the device. I don't know what I'm missing or doing wrong. Any suggestion is welcome
