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Altera_Forum's avatar
Altera_Forum
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16 years ago

How to keep logic not being optimized away?

Hi guys: For some applications, I need insert some logic cells in my design. How to keep these logic? Another question is anyone know what is the delay range of one logic cell? 4 ns? or...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Another question is that if i use lcell as the delay chain, i found that the cpld device doesn't have enough resoures ~0~.

Just like what Harald said, it seems that we should find other ways to implement it.