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Thanks for your extended explanation, I'm quite new to this and this is really helpful.
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You're welcome.
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For this new project we want to go further from another project. But now with interface Y instead of interface X, more memories... In theory we have enough pins but it's close. Therefore, I wanted to check this with the pin planner. I removed all code from this old project and changed the top level interface. Adding more and more pins with some basic code or a megawizard design behind it. Some things got synthesized away and to prevent this, I created this thread. In the meanwhile I got to know virtual pins which also helped preventing things from getting synthesized away.
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Another way to stop the synthesis tool from removing components is to use synthesis constraints (keep and no prune). Though eventually its better to create a design that works, eg., a Qsys system, add stuff to that system, simulate it, and then synthesize it. At least then you can be 100% sure your resource estimates are legitimate ... unfortunately it requires more effort.
Cheers,
Dave
Honored Contributor
