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Altera_Forum
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12 years ago

How to keep all top level signals for mapping to pins (feasibility study)

Hello, For a feasibility study, I have to see if we can use a certain FPGA. Mainly seeing if we can fit all the needed signals on the pins. For that I took another project on which the new...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi Dave,

Thanks for your extended explanation, I'm quite new to this and this is really helpful.

For this new project we want to go further from another project. But now with interface Y instead of interface X, more memories... In theory we have enough pins but it's close. Therefore, I wanted to check this with the pin planner. I removed all code from this old project and changed the top level interface. Adding more and more pins with some basic code or a megawizard design behind it. Some things got synthesized away and to prevent this, I created this thread. In the meanwhile I got to know virtual pins which also helped preventing things from getting synthesized away.

I also ran into trouble with VCCIO and VCCPD. I didn't knew the concept of pre-driver voltage and that they are shared among multiple I/O banks preventing for example the use of 3.3V I/O and 1.5V I/O in the same group.

Once again, thank you for your help!