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I'm using an Arria V and need to interface (a lot of) memories, transcievers and general I/O on 1.5, 2.5 and 3.3V.
So it seems that what I want to achieve is quite hard to do? In theory, all the required pins should fit on the device but I want to be sure. How are people doing this feasability study then?
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Start with a development kit; you don't have to actually buy it, just go through and configure the memory interfaces from scratch, or using their example designs, "reverse engineer" the IP core settings.
For example, the Arria V GT Development Kit appears to be shipping with the non-ES (engineering sample) devices. I have some ideas for a design in an Arria V, and started a couple of example projects using the device on that kit (there's two identical devices).
Create a design for each IP core you want to use, synthesize it, add timing constraints, and get each core to meet timing. Then start combining IP into a single system. For example, each IP could be part of a Qsys system, with an Avalon-MM master that is either a JTAG-to-Avalon-MM bridge or a NIOS II processor, or if you want to simulate, an Avalon-MM BFM master.
The key to FPGA development is to have the top-level design synthesized *before* you actually design a board. Then as you design your board, you can move pins around to ease routing, and re-synthesize the design to make sure you have not made an illegal change to the pin assignments.
Cheers,
Dave
Honored Contributor
