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Altera_Forum
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12 years ago

How to keep all top level signals for mapping to pins (feasibility study)

Hello, For a feasibility study, I have to see if we can use a certain FPGA. Mainly seeing if we can fit all the needed signals on the pins. For that I took another project on which the new...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks for your replies, sorry that mine is late!

I'm using an Arria V and need to interface (a lot of) memories, transcievers and general I/O on 1.5, 2.5 and 3.3V.

So it seems that what I want to achieve is quite hard to do? In theory, all the required pins should fit on the device but I want to be sure. How are people doing this feasability study then?