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Altera_Forum
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12 years ago

How to keep all top level signals for mapping to pins (feasibility study)

Hello, For a feasibility study, I have to see if we can use a certain FPGA. Mainly seeing if we can fit all the needed signals on the pins. For that I took another project on which the new...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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I haven't had a chance to try 13.1 ... I'll re-run the script now.

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Quartus gets to "Fitter router operations beginning", has a message that interconnect usage is 0%, and then goes off into la-la-land; its been 30minutes and its still running (using a CPU core according to the Windows task manager).

So even if you can describe a legitimate design with appropriate "null" IP blocks inserted to preserve pin assignments, there's no guarantee Quartus will actually synthesize it!!!

Cheers,

Dave