How to keep all top level signals for mapping to pins (feasibility study)

Altera has made the creation of a "basic" top-level design, i.e., one which includes all pin assignments, but minimal logic (eg., "blinky LED") very difficult.

For example, transceiver interface pin assignments cannot appear in a top-level design *unless* they connect to a transceiver IP block. This "rule" also applied to transceiver reference clocks. The workaround is to instantiate a transceiver IP block, and hold it in reset.

I was playing with the BeMicro CV (Cyclone V) kit last month and it appears there is a new "rule"; you cannot include pin assignments for the hard memory interface unless they are connected to a hard memory IP instance. I tried using ALTIOBUF components, but Quartus 13.0sp1 would "freeze" and never complete compilation. I haven't had a chance to try 13.1 ... I'll re-run the script now.

Bottom-line is that Altera make using a common top-level entity difficult, but (probably) not impossible depending on your device.

What part are you using, and what pin assignments to interfaces do you need to preserve?

Cheers,

Dave