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Altera_Forum
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12 years ago

How to keep all top level signals for mapping to pins (feasibility study)

Hello, For a feasibility study, I have to see if we can use a certain FPGA. Mainly seeing if we can fit all the needed signals on the pins. For that I took another project on which the new...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

A brute solution which doesn't need any attribute is feeding the N unused input signals into a N input AND or OR port and drive a spare fpga pin with the port output