How to integrate two projects into one?

Hi,

One question I'd have here is what is the structure of your new, combined design?

When I've taken an existing project (with .vhd files containing the design logic) and added other design elements that are to exist at the same level in the design's hierarchy, I've needed to create a new top level unit. You can do this in Quartus, but I decided to do it manually by editing a new .vhd file with the top level E/A and having the other design units (top levels in their own, respective projects) as components in the new design. I then added the elements into the project (menu Project->Add/Remove Files in Project...)

I was then able to quickly locate and resolve any naming or mismatch issues during analysis & elaboration of the new, combined design. In simulation, I then refer to the combined top-level object in the tree view as the root for conducting the simulations. (In my case, I had created a separate project with VHDL TestBench logic that got merged into a project which was the Model under test, and which was the model going out to a Cyc III device).

In my experience, the trick is in adding the new design units to the project, making sure pinout between the projects maps correctly through the top-level unit, and making sure the use of scope prevents any name clashes. But having a new top level under which all the elements exist that you want to merge should alleviate a lot of problems. This experience wouldn't be radically different for Verilog than for VHDL, only that VHDL is more "finicky" about the connectivity.

It is also easy to check the structural correctness of the combined design using the schematic viewer (menu Tools -> Netlist Viewer -> RTL), to see that you have assembled what you want.

This is just another data point for you to consider.

Hope this helps.

cheers,

jim