Forum Discussion
New ContributorHow to instance SDRAM controller in DE10 Lite?
- Clearly ease of use. Works without installing JTAG stack (at least Standalone-Programmer) on the client computer.
Altera/Intel RS232 UART IP uses AVMM interface which I don't need in basic HDL debug logic design. I have simple Rx and Tx code with fixed baudrate (921k) written from the scratch. There's no code I can send you as is, I'll check if I can extract something. There are however tons of UART code on the net.
Super ContributorNo, you can't initialize an off-chip RAM with a .mif. That is for initializing on-chip RAM during device programming only.
YigalB1Thank you.
What about instancing the SDRAM?
Is that doable from the Quartus side? Like other IPs?
- sstrell
Do you mean "instantiating"? If the target device supports it, it will be available in the IP Catalog. If DDR4 does not appear there, then it is not supported, which makes sense for an old DE10 board (Cyclone V I believe). https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1046&PartNo=2#contents
- YigalB1
Yes, I mean instantiating it, and I think I made a mistake: it is probably DDR3 and not DDR4.
Here is what I see in the IP catalog:
I am not sure why PHY is required if this is on board FPGA and connected directly to the FPGA with control signals. I think this IP is not intended for the onboard DDR chip.
Still, assuming there is no SDRAM IP, such a controller can be placed inside the FPGA.
Is there a way to program the SDRAM from the host directly, without using the SDRAM controller on the FPGA?
The target is to use the SDRAM as a large buffer, filling it with data from the host, and then letting the FPGA process this data.
