Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to indicate a clk signal is differential in a MAX 10 FPGA
Hello, I am programming a MAX 10 FPGA and I would like to know how I can tell the device that the clk_in signal I defined in the top module is a differential clock. When compiling the project ...
Altera_ForumHonored Contributor
Honored ContributorI found a solution which was editing the .qsf file instead of using the Pin Planner so I manually told the tool the assignments I need. Thanks for your help anyways!
