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Altera_Forum
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9 years ago

How to indicate a clk signal is differential in a MAX 10 FPGA

Hello, I am programming a MAX 10 FPGA and I would like to know how I can tell the device that the clk_in signal I defined in the top module is a differential clock. When compiling the project ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Did you set the clock input to a differential I/O standard in the Pin Planner? That should automatically enable a _n pin. Is the clock differential in your design's top-level port list?