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Altera_Forum's avatar
Altera_Forum
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18 years ago

how to implement multi-register?

Chip needs control registers,state registers.etc. The cost of Using FFs and muxs to read and write the data is expensive.I once want to use block RAM for my design,but it seem it cant reduce the FFs but also increase RAM.Guys,any suggestion about this?:confused:

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  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    The cost of Using FFs and muxs to read and write the data is expensive.

    --- Quote End ---

    Why do you say these resources are "expensive". FPGAs are rich in logic resources. Unless you've used a very high percentage of logic resources or don't have enough left for anticipated future growth, I wouldn't worry about how "expensive" these resources are.

    --- Quote Start ---

    I once want to use block RAM for my design,but it seem it cant reduce the FFs but also increase RAM.

    --- Quote End ---

    If you are short on available logic resources and have memory resources unused, then there are multiple Quartus settings that can implement some logic in RAM blocks.

    Many of these settings are covered by Tools --> Advisors --> Resource Optimization Advisor --> Logic Element Usage. Some settings in this advisor will reduce the logic resource utilization without using RAM blocks; some are related to moving logic from LEs to RAM blocks.

    If the logic resources are full, then you can map some logic to RAM blocks using Assignments --> Settings --> Fitter Settings --> Physical Synthesis Optimizations --> Perform logic to memory mapping.

    You might have logic that could be implemented in RAM blocks if you do it manually even if the Quartus settings won't do it automatically.
  • Altera_Forum's avatar
    Altera_Forum
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    Putting registers in RAM will only work out if you only need one value from the registers at a time. If you have several registers that control the operation of other logic, then you will need simultaneous access to their values. Flops provide that, RAM does not (well, multiple read ports on a RAM could, but FPGAs are limited to 2 read ports per RAM - and you could actually use several RAMs, but that's costly).

    If your register set is large enough that the read mux is costly, then you can shadow the FFs with a RAM, but only if the FF value changes value only by address controlled writes to the registers. Sometimes this is useful for speed, not just area.
  • Altera_Forum's avatar
    Altera_Forum
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    As far as I remember RAM can be configured as much data bits long as you need..

    imho, you could to instantiate the second RAM block (if you already have such in use) and just to activate read signal forever.. what about this?