How to hold data in a register

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Hi all!

It's probably a naive question but i came from microcontroller's world.

When i write:

DATA_BUF <= DATA_BUS when (some condition)

So if DATA_BUS = 10 and after 5 sec it is 20 , DATA_BUF changes its value accordingly. How can i hold the previous vale in DATA_BUF?

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Hi,

do have any background in digital RTL design? If not, you need to go through some basics.

In Verilog you could write:

wire [7:0] DATA_BUS;

wire CLK;

reg [7:0] DATA_BUF;

always @(posedge CLK) begin

DATA_BUF <= DATA_BUS;

end

This code segment describes a register which stores with the positive edge of the signal CLK the value of DATA_BUS.