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seamusbleu
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3 years ago
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How to handle Stratix10 HPS-to-FPGA bridge ID width mismatch

The h2f_axi_master in the s10_hps has ID widths (AWID/ARID/RID/BID) of 4. I connect it to my custom IP which also has an ID width of 4 but platform designer complains that the ID width must be 5. I...
  • seamusbleu's avatar
    seamusbleu
    3 years ago

    So what you're saying is that there is no solution to this problem - that is not helpful.

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seamusbleu
Icon for New Contributor rankNew Contributor
3 years ago

Link to HPS-to-FPGA Bridge showing ID width is 4. This is also the case for the f2sdramN_data AXI slave buses. I need to connect them up to 3 of my custom IP which also have master ID widths of 4. In this case, I need the f2sdramN_data ID widths to go from 4->6 to accommodate the 3 masters. So the above question(s) applies here as well.