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New ContributorHow to guarantee stable data when altsyncram and state machine use same clock?
ALTSYNCRAM is a synchronous SRAM block, the output data is registered using the outclock. The input data/address/control is registered using the inclock. Connect inclock and outclock to the same source clock to use it as a fully synchronous SRAM. You then just need to meet setup/hold requirements for all the registers and adhere to maximum clock frequency limits for the device (ie, to guarantee SRAM access time met). These are NOT like discrete ASYNC SRAMs which I believe you are comparing them to.
Regular ContributorALTSYNCRAM is a synchronous SRAM block, the output data is registered using the outclock. The input data/address/control is registered using the inclock. Connect inclock and outclock to the same source clock to use it as a fully synchronous SRAM. You then just need to meet setup/hold requirements for all the registers and adhere to maximum clock frequency limits for the device (ie, to guarantee SRAM access time met). These are NOT like discrete ASYNC SRAMs which I believe you are comparing them to.
Joes19Thanks! I just went back into the megawizard and toggled the option to register outputs with input clock. I'll give it another try, don't mind the pipelined outputs if it saves me from a complicated memory write procedure.
