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Altera_Forum
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11 years ago

How to go from time-limited SOF to regular SOF file?

Hi

I have been using several Altera IPs in Open-Core evaluation mode (Quartus 13.1) where I generated time-limited SOF files. After successfully evaluating the design, I recently purchased the IP licenses.

Now do I need to recompile the whole design from the start (ie. synthesis) to generate a NON-time-limited SOF file?

Also do I need to re-run the Qsys HDL generation again as well? Note some of my open-core eval IPs are instantiated in Qsys.

Appreciate the feedback!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I'm pretty sure that:

    a) Yes, you do need to recompile. Extra logic is inserted in the time-limited .sof to cause the timeout. It can't be "removed" because it's just put into an FPGA and it has no idea whether you had the license or not.

    b) I don't think you need to regenerate the QSYS stuff. It's during synthesis when Quartus checks for a license, and if there isn't one, inserts this OCP logic. It's not done in the source(i.e. the QSYS generated code). My experience is I've seen this added, and as soon as we had a license we recompiled and it was gone.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks Rysc for the fast response.

    I'm doing full recompile without rerunning the Qsys generation. By the way, after re-running the synthesis, I'm still seeing the "pzdyqx:nabboc" component listed under the top level project name. I thought that was for the OCP or is it not? I was expecting it to go away.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    It is that logic, so it seems wrong. I would wait for it to finish though, as I've seen legacy stuff show up in the Hierarchy Browser and other windows mid-compile. (When it's through synthesis, look for it in the .map.rpt. If it's there, soemthing's up and the license doesn't seem to be taking.)