How to give phase shift to dqs signal.

With PLL you must use a predefined input frequency, so you can't use a clock which changes depending from mode, unless you want to reconfigure PLL at runtime.

You could generate a fixed clock at the maximum 2x frequency, say 166MHz, then sample dqs at this rate with some logic like this:

mode 4 (83MHz): toggle dqs out pin one clock after dqs in edge

mode 3 (66MHz): toggle pin one or two clocks after dqs in edge

mode 2 (50MHz): toggle pin two clocks after dqs in edge

mode 1 (33MHz): toggle pin 3 clocks after dqs in edge

mode 0 (20MHz): toggle pin 4 clocks after dqs in edge

You will not have an exact 180 degree phase, but I think it would be enough for your purposes. I presume the exactly center aligned constraint is critical only at the 83MHz mode, isn't it?

Cris