Honored ContributorI want to implement phase synchronization after serdes transmission. The recovery clock from CDR is phase aligned with transmitted side's clock after every power cycle. How to do this? Any one can help me for this question?
Honored ContributorMind further elaborate what kind of phase synchronization that you are looking for? Generally in the transceiver channel, there is a phase comp FIFO which will help to compensate for phase different between the transceiver and fabric.
Honored ContributorI want to do the phase alignment between the ref_clk of the transmitted side and the recovery clock of CDR in the receiving side? I only found the frequency synchronization, but the initial phase in the receiving side is not same with the transmitted side. What's wrong for the Altera PHY?
Honored ContributorHonored ContributorAgreed with kaz. Generally in a transceiver application, there will be ppm difference between the upstream and downstream devices. The CDR's recovered clock is depending on the incoming data transition and it is expected to have ppm and phase difference with the local TX clocks.
