Forum Discussion
Altera_Forum
Honored Contributor
10 years agoI don't want to put you off your code but I can't follow it since I have my own simple code below for pwd at any duty cycle, any frequency:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm is
port(
clk : in std_logic;
freq_word : in std_logic_vector(13 downto 0) := "00011001100110";
duty_scaled : in std_logic_vector(13 downto 0) := "10000000000000";
pwm : out std_logic
);
end entity;
architecture rtl of pwm is
signal ptr : unsigned(14 downto 0) := (others => '0');
begin
process(clk)
begin
if(rising_edge(clk)) then
ptr <= ptr + unsigned(freq_word);
pwm <= '0';
if ptr(13 downto 0) < unsigned(duty_scaled) then
pwm <= '1';
end if;
end if;
end process;
end rtl;