how to fix varying pwm along with constant frequency of 20kHz in cyclon 2 ep2c5t144c8

Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity pwm_sti is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

feed_back : in STD_LOGIC_VECTOR (7 downto 0);

driv1_out : out STD_LOGIC;

driv2_out : out STD_LOGIC;

pwm_out : out STD_LOGIC);

end pwm_sti;

architecture Behavioral of pwm_sti is

signal counter_166, counter_166_delay : unsigned(7 downto 0);

signal count_2500clk_cycles : unsigned(11 downto 0);

signal pwm_comp_reg : unsigned(11 downto 0);

signal count_pwm_comp_reg : unsigned(11 downto 0);

signal delta_reg : unsigned(7 downto 0);

signal driv1_out_sig, driv2_out_sig, state_falg : std_logic;

signal counter_1div60_div4, counter_1div60_div4_delay : unsigned(1 downto 0);

begin

driv1_out <= driv1_out_sig;

driv2_out <= driv2_out_sig;

-- pwm generation process

process(clk)

variable pwm_comp_var : unsigned(12 downto 0);

begin

if(clk'event and clk = '1')then

if(reset = '1') then

counter_166 <= (others => '0');

counter_166_delay <= (others => '0');

count_2500clk_cycles <= (others => '0');

pwm_comp_reg <= (others => '0');

count_pwm_comp_reg <= (others => '0');

delta_reg <= (others => '0');

driv1_out_sig <= '1';

driv2_out_sig <= '0';

counter_1div60_div4 <= (others => '0');

counter_1div60_div4_delay <= (others => '0');

state_falg <= '0';

else

pwm_out <= '0';

if(state_falg = '0') then

delta_reg <= unsigned (feed_back);

state_falg <= '1';

else

if(count_2500clk_cycles = "100111000100") then

count_2500clk_cycles <= (others => '0');

counter_166 <= counter_166 + 1;

-- adding value to pwm comp reg

if(counter_1div60_div4(0) = '0') then

pwm_comp_var := resize(pwm_comp_reg, 13) + resize(delta_reg, 13);

pwm_comp_reg <= pwm_comp_var(11 downto 0);

elsif(counter_1div60_div4(0) = '1') then

pwm_comp_var := resize(pwm_comp_reg, 13) - resize(delta_reg, 13);

pwm_comp_reg <= pwm_comp_var(11 downto 0);

end if;

-- after half sine cycle

if(counter_166 = "10100110") then

counter_166 <= (others => '0');

driv1_out_sig <= not (driv1_out_sig);

driv2_out_sig <= not (driv2_out_sig);

pwm_comp_reg <= (others => '0');

end if;

elsif(count_2500clk_cycles = "100111000011") then

count_pwm_comp_reg <= (others => '0');

count_2500clk_cycles <= count_2500clk_cycles + 1;

else

count_2500clk_cycles <= count_2500clk_cycles + 1;

if(count_pwm_comp_reg <= pwm_comp_reg) then

count_pwm_comp_reg <= count_pwm_comp_reg + 1;

pwm_out <= '1';

end if;-- count_pwm_comp

end if; -- 2500clk

-- creating a delay

counter_166_delay <= counter_166;

if ((counter_166 = "01010011" and counter_166_delay = "01010010") or

(counter_166 = "10100110" and counter_166_delay = "10100101")) then

counter_1div60_div4 <= counter_1div60_div4 + 1;

end if;-- counter_166

-- creating a delay

counter_1div60_div4_delay <= counter_1div60_div4;

if(counter_1div60_div4 = "00" and counter_1div60_div4_delay = "11") then

delta_reg <= unsigned (feed_back);

end if; --counter 1 div 60 div 4

end if; -- state falg

end if; --reset

end if; -- clk

end process

end Behavioral;