How to find the precision/accuracy of system clock on Cyclone III starter board

Question

Hi,

I'm a student who has just begun to use FPGAs. How can I find the precision and accuracy of the 50 MHz system clock of the Cyclone III Starter Board? I've looked at the User Guide and at other web documentation but I haven't been able to find this particular information.

Thank you so much if you can respond.

altera_forum · Answer

There should be a bill of materials somewhere in the documentation for the board. Find the manufacturer's part#  for the 50MHz oscillator and then find a data sheet for that part. The data sheet will give you the information you need.

altera_forum · Answer

--- Quote Start ---

I'm a student who has just begun to use FPGAs. How can I find the precision and accuracy of the 50 MHz system clock of the Cyclone III Starter Board?

--- Quote End ---

Perhaps a more important question is, "Why are you interested in that parameter?"

Most cheap oscillators will have specifications like 50MHz with some parts-per-million (ppm) tolerance ... Mouser has a pull-down menu with the PPM tolerance ....

http://www.mouser.com/passive-components/frequency-control-timing-devices/oscillators/standard-clock-oscillators/_/n-7jdva?p=1z0wo83z1z0z7ym

If you really had a "precision" application, then the on-board oscillator might not be what you should use? For example, you might be better off connecting your board to an externa clock source that is generated by a synthesizer.

Describe your concern or interest, and people can chime in with advice.

Cheers,

Dave

altera_forum · Answer

Thank you both!

Using the BOM linked to on this page: http://www.linear.com/solutions/5129

I found this: http://www.digikey.com/product-detail/en/ecs-inc/ecs-3953c-500-tr/xc726ct-nd/274086

Frequency Stability = ±100ppm

Forum Discussion

How to find the precision/accuracy of system clock on Cyclone III starter board

3 Replies

Recent Discussions

Cyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memory

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

System PLL of Agliex5 PCIE example design cannot be locked after configuration

JTAG Chain Broken on Agilex 7-I Dev Kit

Request for Cyclone V Pinout File Information