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I suggested:
always @ (posedge clock)
begin
if (Enable)
begin
if (din > max_val)
begin
max_val <= din;
Q_val <= Q;
end
Q <= Q + 1;
end
end
you need to take care of verilog syntax and rules as I am not good at it. You also need to take care of address latency.
I also thought you are reading from memory but your code suggest are just writing to an array from din?? so which is'it? Anyway the code for din above should work in principle. what you do with din before/after is your focus.
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Thank you Kaz for your time :)
I have tried the codes below, both with mem_array and without mem_array gave the same results which are wrong... (as picture attachment)
module absolute(clock,Enable, d_in, max_value, max_location) ;
input wire clock;
input wire Enable;
input wire [9:0] d_in;
output reg [9:0] max_value;
output reg [2:0] max_location;
reg [9:0] max_val_tmp;
reg [2:0] Q;
//reg [9:0] mem_array [0:7];
initial
begin
max_val_tmp = 0;
end
always @ (posedge clock)
begin
if (Enable)
begin
//mem_array[Q] <= d_in;
if (d_in > max_val_tmp)
begin
max_value <= d_in;
max_location <= Q;
end
Q <= Q + 1;
end
end
endmodule
**p.s. I need to write d_in into mem_array[Q] so that i can keep track on its location right?
**another way i found something:
"
develop a verilog model for a peak detector that finds the maximum value in a sequence of 10-bit unsigned integers. a new number arrives at the input during a clock cycle when the data_en input is 1. if the new number is greater than the previously stored maximum value, the maximum value is updated with the new number; otherwise, it is unchanged. the stored maximum value is cleared to zero when the reset control input is 1. both data_en and reset are synchronous control inputs."
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