Forum Discussion
Altera_Forum
Honored Contributor
12 years agoI suggested:
always @ (posedge clock)
begin
if (Enable)
begin
if (din > max_val)
begin
max_val <= din;
Q_val <= Q;
end
Q <= Q + 1;
end
end
you need to take care of verilog syntax and rules as I am not good at it. You also need to take care of address latency. I also thought you are reading from memory but your code suggest are just writing to an array from din?? so which is'it? Anyway the code for din above should work in principle. what you do with din before/after is your focus.