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I have written the code in vhdl, which should work provided you look after type issues(signed...etc).
You can write verilog on same basis.
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Hi Kaz, here is my code... but it's wrong... can you figure out my mistake?
module absolute(clock,Enable, d_in, max_value) ;
input wire clock;
input wire Enable;
input wire [9:0] d_in;
output reg [9:0] max_value;
reg [9:0] max_val_tmp;
reg [2:0] Q;
reg [9:0] mem_array [0:7];
initial
begin
max_val_tmp = mem_array[0];
end
always @ (posedge clock)
begin
if (Enable)
begin
mem_array[Q] <= d_in;
if (mem_array[Q] > max_val_tmp)
begin
max_value <= mem_array[Q];
end
else
begin
max_value <= max_val_tmp;
end
Q <= Q + 1;
end
end
endmodule
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