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Honored Contributor
Honored ContributorHow to do the timing constrain of the clolks of ALTCLKCTRL
I had instanced a ALTCLKCTRL IP core in my project .The ALTCLKCTRL IP core has two clocks input ports and one output ports, the one is 125MHz(inclk0),the other one is 48MHz(inclk1). So How can I do ...
Altera_ForumHonored Contributor
Honored ContributorSo the entire design needs to work at 125MHz. Quartus will (should) realise this if you constrain the clocks as you have.
Quartus can work out that the read side of each FIFO needs to operate at 125MHz (as well as 48MHz). TimeQuest will report timing against both 125MHz & 48MHz clocks. It's (perhaps) likely to meet timing at 48MHz. However, the same read side logic may not meet timing at 125MHz. TimeQuest will report timing for the read side logic against both source clocks. Cheers, Alex
